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| 供应商 | Synopsys |
|---|---|
| 型号 | 6G PHY in TSMC (16nm) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Supports 1.25 to 6.25 Gbps data rates Multi-lane PHY supporting x1, x2, and x4 macro configurations Supports PCI Express 2.1, SATA 6G, SGMII, XAUI, CEI-6G specifications Supports x1 to x16 macro configurations Superior signal integrity enabled by adaptive continuous time linear equalizer (CTLE) and Feed Forward Equalization (FFE) Lowest active and standby power supporting power management, power gating, and novel transmission design Spread Spectrum Clock (SSC) Reference clock sharing for aggregated macro configurations Supports IEEE 1149.6 AC Boundary Scan Wirebond or flipchip packaging with flexible bumps; Supports -40°C to 125°C Tj |
| 详情页 | View more |
| 附件名称 | dwc_multi_protocol_6g_phy_ds.pdf |
| 附件链接 | View more |
The multi-lane DesignWare Multi-Protocol 6G PHY IP is part of Synopsys’ highperformance multi-rate transceiver portfolio, meeting the growing needs for small area, low bill of materials (BOM) cost, low-power consumption in consumer applications. The multi-protocol 6G PHY IP provides low active and standby power while exceeding signal integrity and jitter performance of PCI Express 2.1, SATA 6G, SGMII, XAUI, and CEI-6G specifications. The PHY incorporates advanced power saving features such as PCI Express L1 sub-states power management and power gating in standby mode of operation.
The hybrid transmit drivers support low power voltage mode and high swing current mode for further active power savings. The PHY’s Automatic Test Equipment (ATE) capabilities and wirebond packaging reduce the overall BOM cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.
The hybrid transmit drivers support low power voltage mode and high swing current mode for further active power savings. The PHY’s Automatic Test Equipment (ATE) capabilities and wirebond packaging reduce the overall BOM cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.
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