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| 供应商 | Synopsys |
|---|---|
| 型号 | 32G PHY in TSMC (7nm) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions) Supports back channel initialization, aggregation, bifurcation, and power management Supports both internal and external reference clock connections to the PHY Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal paths Contains embedded 7-, 9-, 11-, 15-, 16-, 23- and 31-bit pseudo random bit sequencer (PRBS) for internal and external loopbacks Fully controllable via the integrated logic core and the test access port (TAP) Embedded BERT and internal eye monitor |
| 详情页 | View more |
| 附件名称 | dwc_multi_protocol_32g_phy_ds.pdf |
| 附件链接 | View more |
The multi-lane DesignWare? Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards, including PCI Express? (PCIe?) 5.0, 1G to 400G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), SATA, and other industry-standard interconnect protocols Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 32G PHY delivers signal integrity and jitter performance that exceeds the standards’ electrical specifications.
The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The PHY provides advanced power management features for both standby and active power. The BERT and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Coding Sublayer (PCS) and Media Access Control (MAC) to reduce design time and to help designers achieve first-pass silicon success.
The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The PHY provides advanced power management features for both standby and active power. The BERT and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Coding Sublayer (PCS) and Media Access Control (MAC) to reduce design time and to help designers achieve first-pass silicon success.
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