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| 供应商 | Synopsys |
|---|---|
| 型号 | 112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Supports full-duplex 1.25 to 112Gbps data rates Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired network infrastructure Supports IEEE 802.3ck and OIF standards electrical specifications Meets the performance requirements of chip-to-chip, chip-to-module, and backplane interconnects Provides comprehensive 112G solution with routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis DAC-based PAM-4 transmitter includes feed forward equalization (FFE) Digital-based receiver consists of analog front-end (AFE), ADC, and digital signal processor (DSP) High-performance receive equalization supports channel loss of 40dB Continuous calibration and adaptation (CCA) algorithms provide robust performance across process, voltage, and temperature variations Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance |
| 详情页 | View more |
| 附件名称 | dwc_112G_ethernet_phy_ds.pdf |
| 附件链接 | View more |
The DesignWare 112G Ethernet PHY IP, an integral part of Synopsys' high-speed SerDes IP portfolio, enables true long reach channels for up to 800G hyperscale data center, networking, and AI SoCs requiring high bandwidth and low latency. Using leading-edge design, analysis, simulation, and measurement techniques, the 112G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3ck and OIF standards electrical specifications. The PHY is small in area, high in performance demonstrating zero BER in greater than 40dB channels, and power-efficient at less than 5pJ/bit.
The 112G Ethernet PHY?s flexible layout maximizes bandwidth per die-edge by allowing placement of square macros in a multi-row structure and along all edges of the die. The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4), Non- Return-to-Zero (NRZ) signaling, and independent, per lane data rates for ultimate flexibility to address broad range of protocols and applications. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithms provide robust performance across voltage and temperature variations. The low jitter PLLs, clock, and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and non-destructive 2D eye monitor capability provide on-chip testability and visibility into channel performance.
Combined with Synopsys' routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 112G Ethernet PHY solution for fast and reliable SoC integration.
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