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供应商	Synopsys
型号	Library of mathematical and floating point (FP) components
类型	Soft IP
到期日	Available on request
源网址	View more
特征	Pre-verified Verilog source code of floating point components Verified C++ models with Synopsys HECTOR? Improved architectures for high-performance operations Includes new compound operators for enhanced power, performance and area Eliminates the need for separate simulation models
详情页	View more
附件名称	dwc_foundation_cores.pdf
附件链接	View more

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详情

Optimized for efficient hardware implementation, the DesignWare? Foundation Cores include a library of mathematical and floating point (FP) components that allow designers to make tradeoffs in power, performance and area to control design precision and meet design requirements. The new flexible floating point (FFP) format enables designers to make tradeoffs in accuracy and share common operations. The components library includes a robust set of atomic operators, compound operations and components that can share stages of the FP operators based on a FFP format. Using the FFP format, designers can implement their own specialized FP components. In particular, the FFP format enables trading off accuracy for better QoR for designs that combine multiple FP operations. This allows designers to explore the area and accuracy of the components to meet their design-specific requirements.

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