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| 供应商 | Digital Core Design |
|---|---|
| 型号 | DSPIS - Serial Peripheral Interface – Slave |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 详情页 | View more |
| 附件链接 | View more |
The DSPIS is a fully configurable SPI ma slave device, designated to operate with passive devices like memories, LCD drivers etc. The DSPIS allows user to configure polarity and phase of serial clock signal SCK. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPIS data are simultaneously transmitted and received. The DSPIS system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. The DSPIS allows the SPI Master to communicate with passive devices. When transmission starts (SS Line goes low) the first portion of data is copied to the address register and then to the ADDRESS bus output, after transmission of the address the DSPIS generates the read signal (RD) and copy DATAI bus contents to the transmitter shift register, and prepare data to be exchanged with SPI Master. During the next data portion transmission DSPIS simultaneously transmits data out and in. When the first data portion is received the DSPIS asserts DATAO bus generates the write signal (WE), then increments ADDRESS bus performs a read operation and prepare another data portion to be exchanged with SPI master. Transmission is ended when the SS line goes high. The DSPIS is a technology independent design that can be implemented in a variety of process technologies. DSPIS is fully customizable, which means it is delivered in the exact configuration to meet users' requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
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