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| 供应商 | Digital Core Design |
|---|---|
| 型号 | DSPI_FIFO - Serial Peripheral Interface – Master/Slave with FIFO |
| 类型 | Soft IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 详情页 | View more |
| 附件链接 | View more |
The DSPI_FIFO is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI_FIFO data are simultaneously transmitted and received. The DSPI_FIFO is a technology independent design that can be implemented in a variety of process technologies. The DSPI_FIFO system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of eight different bit rates for the serial clock.
The DSPI_FIFO automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O), and address SPI slave device to exchange serially shifted data. Error detection logic is included to support interprocessor communications. A writecollision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple master mode fault detector automatically disables DSPI output drivers if more than one SPI devices simultaneously attempts to become bus master.
The DSPI_FIFO supports two DMA modes: single transfer and multitransfer. These modes allow DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
The DSPI_FIFO automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O), and address SPI slave device to exchange serially shifted data. Error detection logic is included to support interprocessor communications. A writecollision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple master mode fault detector automatically disables DSPI output drivers if more than one SPI devices simultaneously attempts to become bus master.
The DSPI_FIFO supports two DMA modes: single transfer and multitransfer. These modes allow DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
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