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| 供应商 | HDL Design House |
|---|---|
| 型号 | DSI Host IP Core - HIP 3500 |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Transfers pixels and data received from DBI or DPI or AHB interface to the peripheral such as display via DSI D-PHY Supports MIPI DSI protocol version 1.02 Supports MIPI DCS version 1.02 Supports MIPI DBI version 2.0 Supports MIPI DPI version 2.0 Supports MIPI D-PHY version 1.0 Supports up to 4 data lanes (minimum is one data lane) and one clock lane Max. data rate 800 Mbps per data lane Supports up to 4 virtual channels Supports command and Video Mode |
| 详情页 | View more |
| 附件名称 | HIP3500.pdf |
| 附件链接 | View more |
DSI (Display Serial Interface) defines protocol between host processor and a peripheral such as Display device, based on MIPI Alliance specifications for mobile devices interfaces, which operates with pixels and command sets specified in the DPI-2, DBI-2 and DCS standards. Its purpose is to send pixels and commands to the peripheral such as Display and receives back pixel or status information from the peripheral. This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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