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供应商	Dolphin Technology
型号	Hardened DDRx SDRAM PHY & LPDDRx SDRAM PHY - TSMC 65nm 65GP 65LP 65ULP 65ULP_EMF
类型	Hard IP
到期日	Pre-silicon
源网址	View more
特征	DDR3/DDR2 PHY IP fully compliant with the DFI 4.0 Specification. LPDDR3/LPDDR2 PHY IP fully compliant with the DFI 4.0 Specification. Support speeds of up to 2133Mbps with 1.8V oxide and 1600Mbps with 2.5V Oxide. IP is split into 2 hard macros: commands, control and address pins and another for 8-bit data bus Compensation controller and Pads are provided for automatic driver and receiver termination impedance calibration Features include slew rate control, Per-bit de-skew, gate training, read and write leveling. JTAG signals also provided for Mentor/Synopsys and LogicVision Built in Self Test with a Pseudo Random Pattern Generator Built with Scannable flops Can be used in wirebond, flip-chip and cup configurations
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附件链接	View more

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详情

Dolphin's hardened DDRx SDRAM PHY and LPDDRx SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST). In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin's DDRx and LPDDRx SDRAM Memory Controller IP.

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