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| 供应商 | T2M |
|---|---|
| 型号 | DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC) |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Supported DRAM type: DDR5/DDR4/LPDDR5 Maximum controller clock frequency of 675MHz resulting in maximum DRAM data rate of 5400MT/s for DDR5 Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 3200MT/s for DDR4 Maximum controller clock frequency of 600MHz resulting in maximum DRAM data rate of 4800MT/s for LPDDR5 Interface: POD11/POD12/LVSTL05 Data path width scales in 8-bit increment Four modules for flexible configuration: CA/DQ_X16/DQ_X8/ZQ Programmable output impedance (DS) Programmable on-die termination (ODT) |
| 详情页 | View more |
| 附件链接 | View more |
The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput. PHY functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL. The Combo PHY IP is also able to run on DDR4, DDR5, LPDDR5 modes separately.
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