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| 供应商 | T2M |
|---|---|
| 型号 | DDR 4/3 Memory Controller IP - 2400MHz |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Support s DDR 4 /DDR3 SDRAM 16 bit s width , Single Channel DDR 4 /DDR3 SDRAM Interface . 16 bits for per channel, could support 2 x8 bits DDR3, but could not support 2 x8 bits DDR4. Memory Clock up to 6 66 MHz, DFI Clock up to 666 MHz . Support DDR3 800/1066/1333/1600 /1866/2133; DDR 4 1866/2133/2400/2666. Support s Continuous Request Supports independent Single channel Arbiter and Controller: s eparate registers to 4 registers: Should use 32bits System Reg in N OC Support SW DDR training Support DDR IO loopback test |
| 详情页 | View more |
| 附件链接 | View more |
This memory controller supports DDR3/4 SDRAM. DDR3/4 memory controller is a high-speed interface used for data read/write between internal engine and outside SDRAM bus, and transfers the internal signal to meet the SDRAM specification.
The DDR3/4 memory controller includes several Sub-Arbiters , Main-Arbiter and Controller module.
Sub-Arbiter supports 4 masters. Sub-Arbiter would be placed in partition or in memory controller. Main-Arbiter supports 16 masters. The memory arbiter will do arbitration one all the masters?’???￠?’?￠￠￠?…????’?￠￠￠?…??￠ (internal engines) request and send those request to DDR (Double Data Rate) controller.
The DDR (Double Data Rate) controller will convert the internal request to DRAM chip protocol for data read/write. The DDR controller also implements the DRAM refresh, DRAM dynamic power down, DRAM Scramble and DRAM Private Usage functions
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