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| 供应商 | Arm |
|---|---|
| 型号 | DDR3/2 IO and PLL FC - TSMC 65nm GP |
| 类型 | Hard IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | DDR3 - 1.5V Drive, 1.0V Core Interface?'?￠￠￠??????…?? DDR3 - Up to 1.6Gb/s operation DDR2 Compatibility Output and input dynamic impedances calibration Bi-directional clock included Low Ground Bounce PLL Ideally suited for precision clock applications Input frequency range: 20-400MHz Output frequency range: 50-800MHz 1.0V Digital supply, 2.5V Analog supply Programmable feedback divider and test bypass system Deskew function included No external components or adjustments necessary due to internal loop filter Lock detect Typical power dissipation: 4mW Very low jitter |
| 详情页 | View more |
| 附件链接 | View more |
ARM® Artisan® 65nm GP DDR3/DDR2 I/O high speed transceiver is designed to interface with various SDRAM designs, resulting in system flexibility, reliability, and cost reduction. Supporting up to 1.6 Gb/s transfer rates with DDR3, this DDR I/O provides flexible voltage signaling levels, enabling interface to either DDR2 SDRAMS (1.8V) or DDR3 SDRAMS (1.5V). The Artisan Combo I/O Library also contains a robust ESD architecture and noise isolation to protect reliability, and extensive tool support to ease integration and SoC implementations. To further ensure reliability, a calibration pad is implemented to allow for dynamic calibration of the output/input impedances for a variety of applications. For DDR2 applications, there is also On Die Termination (ODT) available to eliminate the need for external board resistors for minimized chip area with support for Circuit Under Pad (CUP), and reduce cost. The Artisan DDR3 DDR2 Combo I/O Library delivers seamless integration with Artisan I/O, and QA validation to reduce time to market. The Artisan 65nm GP DDR3/DDR2 I/O is the optimum I/O interface for flexibility, reliability, and lower overall system cost. The ARM® Artisan® Deskew Phase Locked Loop (PLL) is a two output, programmable, frequency synthesizer macro cell designed specifically for clock generation. The Deskew PLL ensures accurate frequency optimization and is designed to remove the skew between the output of a clock and the clock reference. This PLL-based frequency synthesizer generates robust signals from 100MHz to 800MHz using an internal loop filter and active bandwidth regulator, providing maximum noise immunity and minimum jitter. Electrically and physically tuned to the TSMC 65nm GP process, the Artisan PLL provides optimum frequency operation and power consumption for precise, dependable implementations.
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