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供应商	Arm
型号	DDR3/2 1.8V gate oxide PHY - TSMC 40nm G
类型	Hard IP
到期日	In Production
源网址	View more
特征	DDR3 or DDR2 modes & signaling rates up to 1600Mbps and 1066Mbps, respectively x32 or x16 data path interface PVT compensation and timing calibration At speed BIST, scan insertion & Loopback test Dynamic read detection and training Various power-down modes Low jitter with superior noise rejection Read and write leveling up to 500ps skew delta (pt-to-pt 5 DRAM bus) o Implemented using 0.9V RVT core devices and 1.8V gate oxide IO devices Supports both wire-bond and flip-chip packaging
详情页	View more
附件链接	View more

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详情

The ARM® Artisan® DDR3/2 Physical Memory Interface (PHY) is a drop-in hard macro which minimizes die size, speeds time-to-market, and reduces risk. The hard macro is implemented as a flexible pad ring configuration, enabling optimal pad ring placement and die area optimization. The 1066Mbps DDR2 or 1600Mbps capable DDR3 interface reduces design time with its JEDEC-compliant DDR signaling and industry standard DFI interface, enabling seamless integration with DDR memory controllers and SDRAM chips. The DDR3/2 Physical Interface is designed with a robust ESD architecture and PVT compensation. The Artisan DDR3/2 PHY maintains high signal integrity, low jitter, and superior noise rejection in a complete silicon-proven design, providing SoC designers with a flexible, low risk, drop-in DDR PHY solution.

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