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| 供应商 | CAST |
|---|---|
| 型号 | SENT/SAE J2716 Controller Core |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | SENT/SAE J2716 Receiver & Transmitter Fast and Slow Channel Transmit or Receive CRC generation for Transmitter, and CRC checking for Receiver All types of SENT Frames Programmable data length (4 to 24 bits) for Fast Channel Frames Short (8-bit data) and Enhanced (12- or 16-bit data) Message Formats for Slow Channel Optional Pause Pulse with programmable length Supports inverted SENT protocol Short PWM Code (SPC) Receiver & Transmitter Allows up to four sensors (transmitters) to use the same physical SENT connection Programmable master trigger pulse length Ease of Integration 32-bit APB interface, and comprehensive set of interrupts Programmable 4-bit clock divider and high precision 16-bit clock pre-scale Receive and Transmit FIFO of configurable size for Fast Channel data Run-time programmable configuration registers Synthesis-time defined reset values for all registers, enables data transmit without control from host processor LINT-clean, single-clock domain, scan-ready design |
| 详情页 | View more |
| 附件链接 | View more |
The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and also the industry de-facto standard Short PWM Code (SPC) protocol, and can be used for conveying data from one or multiple sensors to a centralized controller using a single SENT line. The CSENT core can be configured as a Transmitter and/or as a Receiver, and therefore it is suitable for adding a SENT interface to devices transmitting sensor data or to controllers receiving sensor data. It provides access to its control, status, and data registers via a 32-bit APB bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. The core allows for Transmitter operation without requiring any external programming or control. The reset values for all its control registers are defined at synthesis time, and at run time the system only needs to write sensor data to the core. The CSENT core is designed with industry best practices. The core contains no latches or tri-sates, and is fully synchronous with a single clock domain. The core is available in Verilog RTL or as targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.
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