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供应商	Cadence
型号	Audio data transport
类型	Soft IP
到期日	Silicon proven
源网址	View more
特征	MIPI-compliant initiator controller with multi-lane capability Configurable port, FIFO, and interface features Multi-entry command FIFO for READ/WRITE/PING commands Arm? AMBA? AHB-Lite interface for control register access Support for Bulk Register Access (BRA) and Bulk Payload Transport (BPT) Isochronous, TX- or RX-controlled, or fully asynchronous transport Bus command ownership - BREQ/BREL handshake Automatic PING generation Bi-directional FIFO-based physical data ports for low-latency audio Flexible frame structure
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附件链接	View more

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详情

The Cadence? IP Family for MIPI? Protocols delivers area-optimized interface IP with the low power and high performance required for today’s leading-edge devices. One member of this family is the Cadence Initiator Controller IP for MIPI SoundWireSM v1.2, providing low-cost, low-power connectivity for audio data transport and control. Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. The Controller IP is engineered to quickly and easily integrate with other MIPI compliant IP. The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of Interface, memory, analog, and system and peripheral IP.

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Controller for MIPI Soundwire-ip-19541