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BT Dual Mode 5.3 HW Linklayer / BaseBand Controller IP-ip-21083
￥10,000.00
| 供应商 | T2M |
|---|---|
| 型号 | Bluetooth Dual Mode v5.3 Baseband Controller IP (Silicon proven IP) |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Software Memory footprint (ARM Cortex M0/M3): ROM ~ 300KB ; RAM ~ 112 KB Combined Hardware gate count : 250 k gates Arbitration logic implemented in hardware and assisted by software Baseband and LE LL Accelerator Discovery / Connection / Role Switch procedures Baseband level flow control, ACK handling & retransmissions Power Save: Sleep mode - clock shut down for core hardware modules, except clock & power management block. Deep sleep mode - clock shutdown to all modules. Bluetooth clock is maintained in 32KHz domain. External RF modem chip can also be shutdown. Shutdown Entire baseband clock can be shutdown by firmware. External RF modem chip can also be shutdown. Enables power gating. |
| 详情页 | View more |
| 附件链接 | View more |
This Baseband Controller IP core is a composite HW-FW implementation of the Classic Bluetooth specifications and Bluetooth Low Energy v5.3 Specifications.
Compatible with the standard Bluetooth HCI, it can be used with any Bluetooth dual mode 5.3 host software protocol stack and profiles, either split around the HCI so that the lower layers and upper layers can run on different processors or systems, or combined together to run on the same processor to make a fully hosted solution.
The feature set for supporting headset solution (including TWS) has been prioritized.
Will support 2 connections Power Considerations
The IP will provide the hooks to ensure power save mechanisms in the SoC
Power gating, clock gating and maintaining a low power domain during sleep are basic hooks
Protocol based features like adaptive window widening and slave latency will be supported.
The IP has always been architected to minimize the uptime of RF
Compatible with the standard Bluetooth HCI, it can be used with any Bluetooth dual mode 5.3 host software protocol stack and profiles, either split around the HCI so that the lower layers and upper layers can run on different processors or systems, or combined together to run on the same processor to make a fully hosted solution.
The feature set for supporting headset solution (including TWS) has been prioritized.
Will support 2 connections Power Considerations
The IP will provide the hooks to ensure power save mechanisms in the SoC
Power gating, clock gating and maintaining a low power domain during sleep are basic hooks
Protocol based features like adaptive window widening and slave latency will be supported.
The IP has always been architected to minimize the uptime of RF
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