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| 供应商 | Arm |
|---|---|
| 型号 | 180MHz ARM968E-S processor core w/o cache. (Area Opt) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | 32/16-bit RISC architecture (ARMv5TE) 32-bit ARM instruction set for maximum performance and flexibility 16-bit Thumb instruction set for increased code density Low latency AHB-lite bus master interface Low latency AHB-lite bus slave DMA interface Configurable Tightly Coupled Memories (TCMs) Dual banked data TCM EmbeddedICE-RT logic for real-time debug ETM interface for Real-time trace capability with ETM9 |
| 详情页 | View more |
| 附件链接 | View more |
The ARM968E-S macrocell is a fully synthesizable 32-bit RISC core aimed specifically at embedded real-time applications, and is the smallest, lowest power ARM9E family core to date. The core implements the ARMv5TE instruction set and features an enhanced 16 x 32-bit multiplier capable of single cycle MAC operations, and 16-bit fixed point DSP instructions to accelerate signal processing algorithms and applications. The ARM968E-S core has separate directly connected instruction and data tightly coupled memory (TCM), which have flexible sizes. The ARM968E-S also features a dedicated AHB-lite slave Direct Memory Access (DMA) port and dual banked data TCM to enable the core and a DMA controller to share access to TCM. The ARM968E-S supports ARM's real-time trace technology with the optional ETM9 Embedded Trace Macrocell. The core includes a low latency AMBA AHB-lite bus-compliant master interface for efficient connection to peripheral devices and for rapid response to system interrupts.
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