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| 供应商 | Arm |
|---|---|
| 型号 | ARM1136JF-S processor with cache |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Powerful ARMv6 instruction set architecture Energy-saving power-down modes High performance memory system Vectored interrupt interface and low-interrupt-latency mode speeds interrupt response and real-time performance Optional Vector Floating Point coprocessor (ARM1136JF-S) ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models |
| 详情页 | View more |
| 附件链接 | View more |
The award-winning ARM1136J-S and ARM1136JF-S deliver up to 660 Dhrystone 2.1 MIPS in 0.13u process. Both cores feature the ARM v6 instruction set with media extensions, ARM Jazelle technology for efficient embedded Java execution, ARM Thumb code compression, and optional floating point coprocessor. Media processing extensions offer up to 1.9x acceleration of media-processing tasks such as MPEG4 encode. Instruction and data cache sizes are configurable, and optional Tightly Coupled Memories can be added to accelerate interrupt handling and data-processing. These cores feature AMBA 2.0 AHB interfaces compatible with a wide range of system IP and peripherals. The ARM1136JF-S also features an integrated floating point coprocessor, which makes it particularly suitable for embedded 3D-graphics applications. The ARM11 core has been developed and integrated in parallel with the ARM11 PrimeXsys Platform to ensure a fully compatible, high performance, extendable system solution. As a result, the ARM11 PrimeXsys Platform provides the optimum route to the efficient and rapid implementation of an ARM11 core-based design.
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