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| 供应商 | Arm |
|---|---|
| 型号 | ARM1026EJ-S processor core with cache |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | 32-bit performance-optimized processor core implementing the ARM, Thumb, DSP, and Java ISAs (v5TEJ) Full MMU support for Windows CE, Linux, Palm OS, Symbian OS, and Java OS Full MPU support for a broad range of real time operating systems Separate instruction and data caches Separate instruction and data TCM Parity protection support on SRAM arrays for maximum field reliability Dual 64 or 32-bit AMBA AHB bus interfaces Direct-attach vector interrupt controller interface for improved interrupt response Support for optional vector floating point and embedded trace coprocessors EmbeddedICE-RT logic for real-time debug |
| 详情页 | View more |
| 附件链接 | View more |
The ARM1026EJ-S macrocell is a fully synthesizable processor delivering a new level of performance, functionality and flexibility to enable innovative SoC applications. A Jazelle Technology enhanced 32-bit RISC ARM10EJ-S CPU with extensive 64-bit internal bussing is combined with configurable instruction and data caches, configurable tightly coupled memories (TCM), support for parity protection on SRAM arrays, memory management and protection units (MMU and MPU), vector interrupt controller interface, advanced vector floating point support and dual 64/32-bit configurable AMBA AHB system interfaces. The ARM1026EJ-S core implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier. The ARMv5TEJ instruction set includes 16-bit fixed point DSP instructions to enhance performance of many signal processing algorithms and applications as well as supporting Thumb and Java bytecode execution.
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