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| 供应商 | CAST |
|---|---|
| 型号 | AES-XTS for Storage Encrypt/Decrypt Core |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm Implemented according to the IEEE P1619￠"?￠/D16 standard NIST Certified Capable of processing 128 bits/cycle Employs user-programmable key size of 128 or 256 bits Two architectural versions: The AES-XTS-X version is smaller and can process 128 bits/cycle for all key sizes The AES-XTS-X2 version can process 256 bits/cycle for all key sizes Arbitrary IV length Works with the integrated key expansion function Simple, fully synchronous, reusable design Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices Complete deliverables include test benches, C model and test vector generator |
| 详情页 | View more |
| 附件链接 | View more |
The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths.
Two architectural versions are available to suit system size and throughput requirements. The XTS-X is more compact and can process 128 bits/cycle independent of the key size. The XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path.
The AES-XTS cores are fully synchronous design and have been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.
Two architectural versions are available to suit system size and throughput requirements. The XTS-X is more compact and can process 128 bits/cycle independent of the key size. The XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path.
The AES-XTS cores are fully synchronous design and have been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.
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