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AES-P, Programmable Block-Cipher AES Encryption-ip-18980
￥10,000.00
| 供应商 | ALMA Technologies |
|---|---|
| 型号 | AES Encryption / Decryption with programmable Block-Cipher Mode |
| 类型 | Soft IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | Compliant to Advanced Encryption Standard (AES) (FIPS PUB 197) Run-time programmable encrypt or decrypt Run-time programmable cipher-key size: 128, 192, 256-bit Run-time programmable block-cipher mode: ECB, CBC, CFB, OFB, CTR AES32-P: Processes each 128-bit block in 44/52/60 clock cycles for 128/192/256-bit cipher keys respectively (ECB mode) AES128-P: Processes each 128-bit block in 11/13/15 clock cycles for 128/192/256-bit cipher keys respectively (ECB mode) Includes Round Key Table for storage of Round Key values Fully stallable input and output interfaces, ideal for streaming applications Optional Key Expansion module for generation of Round Key values Single clock domain and strictly positive edge triggered design using only D-type FFs |
| 详情页 | View more |
| 附件链接 | View more |
The Alma Technologies AES-P IP core family implements the FIPS-197 Advanced Encryption Standard, and can be programmed to either encrypt or decrypt 128-bit blocks of data, with 128- bit, 192-bit or 256-bit cipher-key. The Block-Cipher mode of operation can also be run-time programmed to one of: ECB, CBC, CFB, OFB, CTR.
The AES-P core is available in two variations, Standard AES32-P and Fast AES128-P.
AES32-P has a 32-bit internal data path and the AES128-P has an 128-bit internal data-path. The AES32-P core is more compact in size but with lower throughput than the AES128-P core. For the AES32-P core, 44/52/60 clock cycles are required to encrypt or decrypt an input block with a 128/192/256-bit cipher key respectively. 11/13/15 clock cycles are required for the AES128-P core.
During each step of the encryption / decryption processing, the core requires a previously calculated Round Key Value derived from the cipher-key using a key expansion algorithm. The Round Key Values must be stored to the internal Round Key Table, from which the core acquires the appropriate for each processing step value.
Alternatively, instead of directly programming the Round Key Values to the Round Key Table, an optional Key Expander module is provided. The cipher-key is given to the core and the Key Expander module automatically calculates the Round Key Values and fills the internal Round Key Table.
The AES-P cores include run-time programmable Block-Cipher mode selection. Supported modes are: ECB, CBC, CFB, OFB and CTR.
The AES-P cores are equipped with easy to use fully stallable interfaces both for input and output. These are designed to permit the user's application to pause the produced output data stream when it is not able to receive data, or to pause the input stream towards the core according to data arrival rate.
The AES-P core is available in two variations, Standard AES32-P and Fast AES128-P.
AES32-P has a 32-bit internal data path and the AES128-P has an 128-bit internal data-path. The AES32-P core is more compact in size but with lower throughput than the AES128-P core. For the AES32-P core, 44/52/60 clock cycles are required to encrypt or decrypt an input block with a 128/192/256-bit cipher key respectively. 11/13/15 clock cycles are required for the AES128-P core.
During each step of the encryption / decryption processing, the core requires a previously calculated Round Key Value derived from the cipher-key using a key expansion algorithm. The Round Key Values must be stored to the internal Round Key Table, from which the core acquires the appropriate for each processing step value.
Alternatively, instead of directly programming the Round Key Values to the Round Key Table, an optional Key Expander module is provided. The cipher-key is given to the core and the Key Expander module automatically calculates the Round Key Values and fills the internal Round Key Table.
The AES-P cores include run-time programmable Block-Cipher mode selection. Supported modes are: ECB, CBC, CFB, OFB and CTR.
The AES-P cores are equipped with easy to use fully stallable interfaces both for input and output. These are designed to permit the user's application to pause the produced output data stream when it is not able to receive data, or to pause the input stream towards the core according to data arrival rate.
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