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供应商	Andes Technology
型号	A45 is a 32-bit 8-stage superscalar processor supports RISC-V GCN and P (DSP) extension and MMU
类型	Soft IP
到期日	Available on request
源网址	View more
特征	ï· 8-stage in-order dual issue pipeline with a full-cycle reserved for critical SRAM accesses AndeStar„¢ V5 32-bit architecture, supports RISC-V RV32GCN and P(DSP) Machine(M), User(U), Supervisor(S) privileges, MMU with 32 to 512-entry shared TLB, Sv32 virtual memory translation PMP and PMA with up to 16 regions Advanced Dynamic Branch Prediction Instruction and Data Cache/Local Memory MemBoost - Enhanced Memory Performance AXI bus master port, 4-bit data width, I/D joint or separate bus, and ynchronous N:1 core vs. bus clock ratios Power Management Platform-Level Interrupt Controller (PLIC)
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The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including ?G (?IMAFD ) standard instructions, ?C 16-bit compression instructions, ?P Packed-SIMD/DSP instructions, ?N for user-level interrupts and Memory Management Unit (MMU) for Linux support. It issues two instructions per cycle that significantly increases the performance efficiency that is important for many applications. A45 is also equipped with comprehensive SIMD/DSP instructions that can boost the performance of voice, audio, image and signal processing. Its ?FD extensions support IEEE754-compliance single and double precision floating point instructions as well. It incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. In addition, A45 features advanced low power branch prediction mechanism for efficient branch execution, instruction and data caches, local memories, and ECC error protection. It also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 64-bit bus, rich power management, and JTAG debug and trace interface for software development support.

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