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| 供应商 | Eureka |
|---|---|
| 型号 | PCI Host Bridge (Master, Target & Configuration) core supporting Cardbus and 32-bit & 64-bit PCI bus |
| 类型 | Soft IP |
| 到期日 | In Production |
| 源网址 | View more |
| 特征 | Fully support PCI bus standard 3.0 in 32-bit and 64-bit operations Combined host bridge, bus master, bus target and configuration initiation functions in one core Burst data transfer with zero wait state . Up to 5336Mbyte/sec at 66Mhz Automatic handling of retry, disconnect, abort with auto-restart on target retry and disconnect Different choices of CPU buses and user interfaces Generate standard PCI type 0 and type 1 configuration access Contains all PCI specific configuration registers User defined base address register mapping at run time Multiple clock domains allow CPU bus operate at different frequency from the PCI bus Optimized for ASIC and FPGA implementations in various system environments |
| 详情页 | View more |
| 附件链接 | View more |
The PCI host bridge provides the means for the the host CPU to interface with the PCI bus. This core contains options to support 32-bit or 64-bit PCI bus and with different user interfaces for different CPUs. The host bridge consists of three functions: PCI bus master, bus target and configuration access generation.
A highly efficient and flexible user interfaces with the system CPU and other user defined logics such as DMA and memory controllers. The core utilizes double data buffer design approach which minimizes design gate count and achieve highest possible data bandwidth at the same time.
The host bridge core allows the CPU or user logic to initialize the entire system during power-up reset. Standard PCI configuration initiation as defined by the PCI specification is implemented by the host bridge, and both type zero and type one transactions are supported. The standard PCI configuration with CONFIG_ADDR and CONFIG_DATA registers are implemented in the core.
This IP core provides many features to support flexible system designs. Different CPU buses such as AHB, AXI, PowerPC, PowerQuicc and generic buses are supported. The CPU interface and PCI buses may operate at separate clock domains. Built-in DMA engine can be added to the IP core for high performance data tranfer. Other features such as power management, bus arbitration and Cardbus support are available as well.
A highly efficient and flexible user interfaces with the system CPU and other user defined logics such as DMA and memory controllers. The core utilizes double data buffer design approach which minimizes design gate count and achieve highest possible data bandwidth at the same time.
The host bridge core allows the CPU or user logic to initialize the entire system during power-up reset. Standard PCI configuration initiation as defined by the PCI specification is implemented by the host bridge, and both type zero and type one transactions are supported. The standard PCI configuration with CONFIG_ADDR and CONFIG_DATA registers are implemented in the core.
This IP core provides many features to support flexible system designs. Different CPU buses such as AHB, AXI, PowerPC, PowerQuicc and generic buses are supported. The CPU interface and PCI buses may operate at separate clock domains. Built-in DMA engine can be added to the IP core for high performance data tranfer. Other features such as power management, bus arbitration and Cardbus support are available as well.
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