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| 供应商 | NTLab |
|---|---|
| 型号 | 512-bit EEPROM |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | SMIC EEPROM CMOS 0.18 um High density of memory cells Writing and erasing data by one high-voltage pulse Programming and erase time 2 ms Page writes allowed Data retention over 10 years (endurance 100000 cycles) Low power dissipation in standby and active mode Internally organized 16(bit per word) x 2(word per page) x 16(page) bit Portable to other technologies (upon request) |
| 详情页 | View more |
| 附件名称 | 180SMIC_EEPROM_02_Brief.pdf |
| 附件链接 | View more |
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits (16(bit per word) x 2(word per page) x 16(page)), which is organized as 16 pages of 2 words by 16 bit with single-bit output data and parallel write data.
Write EEPROM page data comes to input D0<15:0> and write by words to latch through the signal SAMPLE, while the signal write in a state of "1". The address of a word written down in latches is defined by two low bits of the bus adr_bl<1:0>.
Set of flags that define the words that will be erased/written to the page is produced by signals set_flag <1:0>. Erasing of words from page, that correspond to the flags, performed by setting a signal BUSY, with the signal ERASE is at state "1". The address of erased page is defined by four high bits of the bus adr_s<15:0>. Value of the bus adr_s<15:0> doesn't change throughout all cycle of deleting (while BUSY = "1").
Data writing from latches to the words of page corresponding to flags, is produced by signal setting BUSY, thus the signal WRITE is in a state .02;€???1.02;€???. The address of writeable page is defined by four high bits of the bus adr_s<15:0>.
Memory is optimized for usage in the industrial and commercial applications, requiring low power consumption and supply voltage.
The device is implemented on technology EEPROM CMOS SMIC 0.18 um.
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