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| 供应商 | Cadence |
|---|---|
| 型号 | UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high perf |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | 16Gbps per pin and supports 12/8/4Gbps subrates High bandwidth, ultra-low latency, superior power efficiency, and low-power modes BIST features ensure Known Good Die (KGD) Sideband for link management and robust training Interoperable between different technology nodes and foundries on the UCIe chiplet ecosystem >5Tbps/mm aggregated bandwidth Redundant remapping capability in advanced package PHY Background calibration during mission mode Comprehensive characterization and test hooks Supports a wide range of advanced package options including, but not limited to, silicon or RDL interposer, local silicon bridge, and fanout |
| 详情页 | View more |
| 附件链接 | View more |
The Cadence? UCIe IP complete solution meets the growing demand for high performance and bandwidth, superior power efficiency, and ultra-low latency interconnect between dies on different foundries and process nodes. The Cadence? 16G UCIe PHY provides an industry chiplet interoperable solution for on-die integration, as it caters to growing system-in-package (SiP) applications. Standard and advanced UCIe PHY options offer flexibility for designers in implementing a wide range of packaging options. The UCIe PHY IP employs Known Good Die (KGD) techniques and is engineered to quickly and easily integrate into any system-in-package (SiP). It is verified with the UCIe Controller IP as part of a complete UCIe subsystem solution, which also includes Cadence UCIe Verification IP (VIP). The Cadence UCIe total solution offers ease of integration of both the PHY and controller IP in an open chiplet ecosystem.
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