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| 供应商 | NTLab |
|---|---|
| 型号 | Programmable CMOS LVDS Transmitter/Receiver |
| 类型 | Hard IP |
| 到期日 | Pre-silicon |
| 源网址 | View more |
| 特征 | TSMC 0.13 um CMOS 3.3 V analog power supply 1.2 V digital power supply 1.2V CMOS input and output logic signals 8-step (3-bit) adjustable transmitter output current (range from 0.75 mA to 6.5 mA) 1.25 Gbps (DDR MODE) switching rates Conforms to TIA/EIA-644 LVDS standards without hysteresis wo receiver cell types: rail to rail and reduced input range Optimized for pad-limited layout design Portable to other technologies (upon request) |
| 详情页 | View more |
| 附件名称 | 130TSMC_LVDS_04.pdf |
| 附件链接 | View more |
LVDS device consists of one common bandgap reference voltage generator, a number of LVDS transmitter pad groups with their bias blocks, and a number of LVDS receiver pad groups (whether rail to rail or reduced input range) with their bias blocks. Also, LVDS transceiver pad groups may be used. In this case, the receiver bias and the transmitter bias blocks should be instantiated for each transceiver pad group. Group size is defined by the corresponding bias output dimension. In the case when desired group size is not the power of 2, several bias blocks should be used, or bias block with size larger than the group size can be instantiated. For example (see fig 1.), to create 6 RX LVDS lines and 30 TX LVDS lines, one LVDSBIASRX4X, one LVDSBIASRX2X, and one LVDSBIASTX32X cells can be instantiated. Two current lines of the LVDSBIASTX32X cell (that are not connected to the LVDS TX pads) should be left open. For the layout design, it is recommended to place bias blocks as close as possible to their corresponding receiver, transmitter, or transceiver pads. It should be noted that all pad cell ground pins in a group, and the corresponding bias block ground pin should be connected together. However, bandgap reference block ground may be connected to the different ground net, as well as different pad groups may utilize different ground nets.
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