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供应商	T2M
型号	12.5G Multiprotocol Serdes IP, Silicon Proven in TSMC 28HPC+
类型	Soft IP
到期日	Silicon proven
源网址	View more
特征	A universal SERDES IP that operation from 1Gbps to 12.5 Gbps Compatible with PCIe/USB3/SATA base Specification Support 40-bit/32-bit/20-bit/16-bit parallel interface Support for PCIe2(5.0Gbps), USB3.0(5.0Gbps) and SATA3(6.0Gbps) Backward compatible with 2.5Gbps for PCIe Backward compatible with 1.5Gbps, 3.0Gbps for SATA Support flexible reference clock frequency Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm Support programmable transmit amplitude and Deemphasis
详情页	View more
附件链接	View more

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详情

The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support for PIPE interface spec, Universal Serial Bus (USB) compliant with USB 3.0, USB 2.0 (USB Highspeed and Full speed), and USB 3.0 compliant with USB 3.0. Support for extra PLL control, reference clock control, and inbuilt power gating control results in lower power usage. Additionally, the PHY is broadly usable for diverse circumstances under varying considerations of power consumption because the aforementioned low power mode option is customizable.

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