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| 供应商 | NTLab |
|---|---|
| 型号 | 10-bit 4-channel 100 MSPS ADC |
| 类型 | Hard IP |
| 到期日 | Silicon proven |
| 源网址 | View more |
| 特征 | TSMC CMOS 65 nm Resolution 10 bit Standby mode (current consumption <50 uA) Rail to rail input range for LVDS receiver Differential full-scale input range peak-to-peak 1 V Differential Non-Linearity 0.79 LSB Integral Non-Linearity 0.94 LSB 66.0 dB SFDR, 54.2 dB SINAD at 50 MSPS and fin = 10.7 MHz 66.3 dB SFDR, 53.0 dB SINAD at 100 MSPS and fin = 10.7 MHz Portable to other technologies (upon request) |
| 详情页 | View more |
| 附件名称 | 065TSMC_ADC_09_Brief.pdf |
| 附件链接 | View more |
The 10-bit 4-channel 100 MSPS ADC employs a high-performance front-end sample-and-hold with differential multi-stage pipelined architecture and output error correction logic. The reference generator, current source and LVDS receiver are also included to provide a complete ADC. The ADC operates with sampling rate up to 100 MSPS and a corresponding input clock up to 200 MHz (input clock is divided by two). The ADC can be configured to achieve addition power saving at low sampling rate, supports standby mode and features the excellent dynamic and static performance, wide bandwidth inputs, low power consumption and compact die area.
The block is designed on TSMC CMOS 65 nm technology.
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