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| 供应商 | Synopsys |
|---|---|
| 型号 | 12G PHY in TSMC (28nm, 16nm, 12nm) |
| 类型 | Hard IP |
| 到期日 | Available on request |
| 源网址 | View more |
| 特征 | Single, dual and quad channels IEEE 802.3 10G and 40G backplane (XAUI, KR & KR4), port side 40G, 100G (CR4 & CR10), and 10G (XFI, SFF-8431/SFI) IEEE 802.3az Electrical Energy Efficient; SGMII, and QSGMII PCI-SIG PCI Express (PCIe) 3.0/2.1/1.1; SATA 6G/3G/1.5G (Rev 3.2) OIF CEI-6G and CEI-11G; CPRI, OBSAI, JESD204B Aggregation (x2 to x16) & bifurcation; Auto-negotiation (AN) and optional forward error correction (FEC) L1 substate power management and SRIS Multi-tap adaptive and configurable continuous time linear equalizer (CTLE) and decision feedback equalization (DFE); Embedded bit error rate (BER) tester and internal eye monitor Built-in self test (BIST) including 7-, 9-, 11 , 15-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker; IEEE 1149.6 AC Boundary Scan |
| 详情页 | View more |
| 附件名称 | dwc_enterprise_12g_phy_ds.pdf |
| 附件链接 | View more |
The multi-channel, multi-protocol DesignWare? Enterprise 12G PHY IP is part of Synopsys’ high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in enterprise applications. Using leading-edge design, analysis, simulation, and measurement techniques, the Enterprise 12G PHY delivers exceptional signal integrity and jitter performance that exceeds the standards’ electrical specifications. The PHY is small in area and provides a low-power, cost-effective solution that supports multiple industry standards to meet the needs of applications with high-speed port side, chip-to-chip, board-to-board, and backplane interfaces.
The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at speed performance. The high-performance analog front-end incorporates power saving features in both active and standby modes of operation.
The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive. The embedded BER tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare? Physical Sublayer cores and the digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.These features reduce both product development cycles and the need for costly field support.
The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at speed performance. The high-performance analog front-end incorporates power saving features in both active and standby modes of operation.
The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive. The embedded BER tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare? Physical Sublayer cores and the digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.These features reduce both product development cycles and the need for costly field support.
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